Product Code Database
In computing, a memory address is a reference to a specific computer memory location in memory used by both software and hardware. These addresses are fixed-length sequences of Numerical digit, typically displayed and handled as signedness integers. This numerical representation is based on the features of CPU (such as the instruction pointer and incremental address registers). Programming language constructs often treat the memory like an array.
A small number of older machines are bit-addressable. For example, a variable filed length (VFL) instruction on the IBM 7030 "Stretch" specifies a bit address, a byte size of 1 to 8 and a field length.
Some older computers () are decimal Numerical digit-addressable. For example, each address in the IBM 1620's magnetic-core memory identified a single six bit binary-coded decimal digit, consisting of a parity bit, flag bit and four numerical bits. The 1620 used 5-digit decimal addresses, so in theory the highest possible address was 99,999. In practice, the CPU supported 20,000 memory locations, and up to two optional external memory units could be added, each supporting 20,000 addresses, for a total of 60,000 (00000–59999).
Some older computers are character-addressable, with 6-bit BCD characters containing a 2-bit zone and a 4-bit digit; the characters in an address only have digit values representing 0–9. Typically some of the zone bits are part of the address and some are used for other purposes, e.g., index register, indirect address.
Some older computers are decimal-word addressable, typically with 4-digit addresses. In some machines the address fields also select index registers, restricting the range of possible address.
Very often, when referring to the word size of a modern computer, one is also describing the size of address space on that computer. For instance, a computer said to be "32-bit" also usually allows 32-bit memory addresses; a byte-addressable 32-bit computer can address 232 = 4,294,967,296 bytes of memory, or 4 gibibytes (GiB). This allows one memory address to be efficiently stored in one word.
However, this does not always hold true. Computers can have memory addresses larger or smaller than their word size. For instance, many 8-bit processors, such as the MOS Technology 6502, supported 16-bit addresses— if not, they would have been limited to a mere 256 of memory addressing. The 16-bit Intel 8088 and Intel 8086 supported 20-bit addressing via segmentation, allowing them to access 1 MiB rather than 64 KiB of memory. All Intel Pentium processors since the Pentium Pro include Physical Address Extensions (PAE) which support mapping 36-bit physical addresses to 32-bit virtual addresses. Many early LISP implementations on, e.g., 36-bit processors, held 2 addresses per word as the result of a cons. Some early processors held 2 and even 3 addresses per instruction word.
In theory, modern byte-addressable 64-bit computers can address 264 bytes (16 ), but in practice the amount of memory is limited by the CPU, the memory controller, or the printed circuit board design (e.g., number of physical memory connectors or amount of soldered-on memory).
Some early programmers combined instructions and data in words as a way to save memory, when it was expensive: The Manchester Mark 1 had space in its 40-bit words to store little bits of data – its processor ignored a small section in the middle of a word – and that was often exploited as extra data storage. Self-replicating programs such as Computer virus treat themselves sometimes as data and sometimes as instructions. Self-modifying code is generally deprecated nowadays, as it makes testing and maintenance disproportionally difficult to the saving of a few bytes, and can also give incorrect results because of the compiler or processor's assumptions about the machine's state, but is still sometimes used deliberately, with great care.
Some systems have a "split" memory architecture where machine code, constants, and data are in different locations, and may have different address sizes. For example, PIC18 microcontrollers have a 21-bit program counter to address machine code and constants in Flash memory, and 12-bit address registers to address data in SRAM.
Mapping logical addresses to physical and virtual memory also adds several levels of indirection; see below.
However, many early computers did not support such a flat memory model — in particular, Harvard architecture machines force program storage to be completely separate from data storage. Many modern DSPs (such as the Motorola 56000) have three separate storage areas — program storage, coefficient storage, and data storage. Some commonly used instructions fetch from all three areas simultaneously — fewer storage areas (even if there were the same total bytes of storage) would make those instructions run slower.
Some segments are implicitly treated as code segments, dedicated for instructions, call stack segments, or normal data segments. Although the usages are different, the segments do not have different memory protections reflecting this. In the flat memory model all segments (segment registers) are generally set to zero, and only offsets are variable.
On the 360/65, on S/370 models without DAT and when running with translation turned off, there are only a flat real address space and a flat absolute address space.
On the 360/67, S/370 and successors through S/390, when running with translation on, addresses contain a segment number, a page number and an offset. Although early models supported both 2 KiB and 4 KiB page sizes, later models only supported 4 KiB. IBM later added instructions to move data between a primary address space and a secondary address space.
S/370-XA added 31-bit addresses, but retained the segment/page/offset hierarchy with 4 KiB pages.
ESA/370 added 16 access registers (ARs) and an AR access control mode, in which a 31-bit address was translated using the address space designated by a selected AR.
z/Architecture supports 64-bit virtual, real and absolute addresses, with multi-level page tables.
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